1. Field of the Invention
The invention relates to a substrate of semiconductor device, and more particularly, to a hybrid-orientation substrate.
2. Description of the Prior Art
Through the decades, ever-increasing silicon CMOS performance has been relying on device scaling, i.e., reducing channel length, gate oxide, and threshold voltage. Today, as very large scale integration (VLSI) technology enters the 65-nm node and beyond, power consumption has become a limiting factor. To circumvent this limitation, novel device structures and materials are widely pursued, such as FinFETs, vertical MOSFETs, high-k dielectric and/or metal gate, and most of all, various approaches for carrier-mobility enhancement. Process-strained silicon channels engineering by film deposition, trench isolation, silicidation and source/drain materials have been introduced in 90-nm technology. Higher carrier mobility from a new channel material, such as Ge, is also under study. Above all, a novel approach commonly referred to as hybrid-orientation technology (HOT) has been derived to improve carrier mobility through wafer and channel orientation optimization.
Despite the fact that HOT has received considerable attention because its fabrication processes are fully compatible with current VLSI technology without additional new materials, there are still many issues of device design and process integration for this new structure. These include device isolation, epitaxial quality and scalability, mixture of silicon-on-insulator (SOI) and bulk devices.